Modeling X7R (+Ceralink) MLCCs in LTspice

Creating models of X7R multilayer ceramic capacitors (MLCC) can be quite a challenge, depending on the effects the model should include.

Laundry list of troubles:

• Capacitance and ESR are a function of DC Bias voltage, frequency and temperature
• Piezoresonances
• Aging

Further aspects of the simulation model:

• Convergence
• Model intended for AC or transient simulation?
• Charge conservation
• Simulation time

Data acquisition:

• VNA
• LCR-meter
• Resonant lines

Manufacturer’s simulation models

Models from TDK, Würth, Murata and Samsung were inspected. The netlist of the better ones are usually encrypted (yes, looking at you Murata).

TDK

Offers three different kinds of models.

• Simple model
• Precise model
• DC Bias model

The netlist of the simple and precise models are open, whereas the DC Bias model one is encrypted.

TDK Simple model

Fixed series resonant point, fixed ESR.

TDK Precise model

Now things get a bit more interesting.

The RC branches allow making the ESR a bit frequency dependent, at least in a certain frequency range. So it is not a fixed value anymore like in the Simple model. The LTSpice plot below illustrates this using the TDK C3216X7R2A105K160AA (1uF, 100V, X7R, 1206).

The precise model (more or less) considers the frequency dependent ESR below the series resonant point, but not beyond. Typically, the ESR value increases again above the series resonant point, which is not reflected in this model. Therefore, loss estimation will then become inaccurate.

TDK DC Bias Model

The netlist for this one is encrypted. In contrast to the two previously introduced models, the DC Bias model considers the DC Bias voltage applied, as the name indicates.

The impact of the DC Bias effect can e.g. be shown by an RC circuit. Increasing DC Bias, will decrease the capacity C, which leads to a smaller time constant R*C, as illustrated in the plot below.

In the frequency domain, the impact can also be shown:

With increasing DC Bias voltage, the capacity decreases, leading to a higher series resonant frequency as indicated in f_res = 1/sqrt(LC).

Würth

The only downloadable model is identical to the TDK simple model.

Murata

Offers two models.

• Static model
• Dynamic model

MLCC used for simulations: GRJ31CR72A105KE11 (1uF, 100V, 1206, X7R)

Static model

It does not consider DC Bias or temperature effects, however the significant amount of lumped elements used allow for a very good ESR modeling.

Dynamic model

Considers temperature and DC Bias effects. The netlist is encrypted. According to the documentation available, it uses a mixture of lumped elements and behavioral sources.

Samsung

Offers three models.

• Static precise model
• Simple interactive model
• Precise interactive model

Static precise

Again, the ESR is modeled well.

Simple and precise interactive model

Both are encrypted, but include temperature and DC Bias voltage in their model.

Comparison of simulation speed in .AC and .TRAN

Using a simple circuit for simulation in time- and frequency domain, a coarse trend in terms of simulations speed can be seen. As comparative parameter, the “total elapsed time” value in LTspice was used. Furthermore, care was taken for similar conditions, meaning same power settings of the PC, no further programs open and so on.

A MLCC with the same parameters was selected from each manufacturer, as written in the table below.

Results:

Measurement- acquiring the data

Common approaches are VNA, LCR meter and resonant line. For more comparable results, the aging effect (approx. 2,5% loss of capacity per decade in hours) can be reset by heating the ceramic capacitor to 150°C for one hour (valid for BaTiO3 dielectrics).

VNA

Limited by the VNA accuracy itself, the calibration may not be accurate enough for low-loss regions of certain capacitors.

For measurements displayed on here, a Rhode&Schwarz ZVL6 VNA in a 2-port shunt configuration was used. The ports of the VNA only tolerate voltages up to 30V and must therefore be protected against high DC Bias voltage applied to the DUT, e.g. by DC-blocking capacitors as shown below.

The HV-voltage source V1 applies the desired DC Bias voltage to the DUT via the resistors R1-R5. The voltage may only be increased or decreased slowly, otherwise voltage jumps would occur, which could couple via the block capacitors and destroy the VNA. The resistors of different high nominal values are necessary to achieve a high impedance over the whole measuring frequency bandwidth. At sufficiently high frequencies, the value of a chip resistor can be as low as 20 % of the nominal value. However, the VNA already has an internal DC blocker, i.e. a capacitor connected in series. With the external DC blocker, two capacitors are now connected in series, whereby the DC bias voltage is divided between the two. This is undesirable, because you have now created another voltage dependency in the circuit.

The question naturally arises as to how accurate the measurement is and how accurate it has to be at all with a DUT tolerance of ±10 %. Basically, there are several parameters that influence the accuracy like the number of measuring points (N), averaging to eliminate random measurement errors, intermeduate frequency bandwidth and so on.

Far more interesting, however, is the question of how the measurement board influences the measurement. A sweep of the board without a DUT gives insights, as shown below.

The influences of the printed circuit board are negligible compared to the component inaccuracies.

Occurring noise can be reduced by making the DC blocking capacitors larger, as seen in the comparison below.

LCR meter

Measurement problems can occur if R is very small compared to Xc (Q factor calculation).

Resonant lines

The DUT forms a resonant circuit together with an inductive line, e.g. microstrip or coaxial. The impedance and Q of the inductive line is known. This setup allows for measurement of capacitors with very high Q. From the resulting resonant frequency and bandwidth, parameters like Q, ESR and C of the DUT can be calculated.

Possible modeling approaches

• Charge equation (mathematical equations)
• Lumped elements (curve fitting)
• Lookup tables, behavioral sources and capacitor equation ic = C*dU/dt
• Combination of several methods

Charge equation (mathematical equations)

A common way to model the decrease of capacitance with increasing DC bias of multilayer ceramic capacitors in LTspice is using charge equations. LTspice allows entering an expression of the form Q=… instead of a fixed value and takes care of the rest. Measuring the capacitance of a real MLCC at different DC bias voltages, adequately interpolating between them and ultimately integrating the obtained expression is a convenient method. Alternatively, by using a vector network analyzer (VNA), the capacitance can be calculated using S11 or S21 parameter. If the model should be useable for both positive and negative applied voltage, the function used for interpolation must be symmetrical to the vertical axis.

The decrease in capacity is shown in the figure below.

Using any curve fitting tool, a continuous polynomial function for capacitance over voltage characteristic can be obtained. Integration over voltage results in an expression for the stored charge inside the MLCC. The resulting charge equation could be used, however it would be valid for positive voltages only. By fitting the polynomial function of charge to a function with odd symmetry, the described limitation will vanish. This can be done by trial and error or using custom equations method in Matlabs curve fitting tool (cftool).

Polynomial function:

   

Function featuring odd symmetry:

   

Fitting it to the data:

As intended, the charge model using the asinh function is valid for both positive and negative voltages using a=2,16*10^-6 and b=c=31. Applying derivation results in an even symmetric function of capacitance vs. voltage.

The resulting equation can be directly used in LTspice:

The resulting voltages over time on both own and manufacturer model are not expected to exactly overlap since the own model is based on measurement results and capacitance tolerance is specified as 10% in the datasheet.

Lumped elements (curve fitting)

Keysight ADS provides allows real time plotting of circuit characteristics while changing the values of lumped elements. Therefore, a predefined lumped element model can be fitted to measured data quite comfortably. Besides the manual fitting, there are also automated options available, like the optimizer, model generators or classic “AmodelB” templates. Different algorithms like gradient, least square etc. can be chosen. I got better and faster results doing the fitting manually.

The piezoresonances and other jumps can be modeled by additional RLC branches using the tune function and a live-updating plot.

This method can be taken further by fitting the curves for each DC Bias voltage point. There will naturally result in different values for the corresponding lumped elements. A polynomial can then be fitted into the varying values versus the applied bias voltage, resulting in expressions like R(U) = … or C(U) = … the value for L will most likely be fixed, as inductance usually does change with voltage or frequency. The expression for C(U) could be realized using a charge equation.

The left branch consisting of R1, L1, and C1 reassembles the main resonance frequency and the right branch with R2, L2 and C2 describes the most significant piezoelectric resonance. By adding further branches, more damped piezoelectric resonances could also be implemented into the model.

Fitting the above lumped element model to the TDK capacitor C3225X7R2A225K230AM at 5 different DC Bias voltages:

The resulting values of the used discrete components, determined by curve fitting procedure, are displayed in the table below:

The next step is to implement those findings into LTspice models. The same circuit is built in LTspice, modeling the capacitors using a charge equation approach. For the sake of simplicity, C2 is considered constant with a value of 33 nF. The only value changing in the piezo-branch is the ohmic resistance. This can be easily handled by creating a voltage dependent resistor in LTspice. The continuous function is obtained by fitting the data points for R1 from the table into a polynom.

The resulting behavior matches the measurement closely, shown in the plot below.

Lookup tables with capacitor equation

Source for this method is https://www.youtube.com/watch?v=jTwsNkd21pc

The transient behavior of the voltage-dependent capacitor can also be described with a lookup table as an alternative to specifying the charge equation. In this table, pairs of values are stored, for example the capacity of a capacitor depending on the DC bias voltage. This allows the measurement to be implemented in LTspice relatively simply and time-efficiently (depending on the number of measurement points to be entered).

Using again the C3225X7R2A225K230AM capacitor from TDK and measuring its value at different DC bias voltages, the following data is achieved:

Schematic:

The circuit consists of three elements. The AC voltage source V1 with variable DC offset, the voltage source V2, which acts here only as a current meter and the controlled current source B1 with the lookup table stored there. The relation ic = C*dU/dt is directly applied to the controlled current source B1. The values for the capacitance C are taken from the table. A linear interpolation is automatically performed between two pairs of values. Since in the real measurement measured in 25 V steps from 0V to 100V, the DC offset of the voltage source V1 is also swept from 0 to 100 V in 25 V intervals. To ensure a good approximation of the capacitance also in the range of linear interpolation, the smallest possible voltage intervals should be selected for the measurement.

   

Solving for C:

   

Plotting vs DC bias voltage. The linear interpolation between the measuring points (0V, 25V, 50V,…) is clearly visible.

Now the model is compared to the manufacturer’s model using the schematic shown below.

Resulting in the following plot:

Using the lookup-table-model in a simple RC circuit and plotting the voltage across the capacitor:

s2spice.exe

The small program s2spice.exe by Helmut Sennewald allows the conversion of measured .s2p files into a .lib file, which can then be imported into LTspice and used for e.g. the comparison of the real measurements to a model in a single plot.

The corresponding circuit could look like this, where the S-Parameter of the measured component are compared to the manufacturer’s model. In this case it is a 100nF, X7R, 1206, 250V MLCC from KEMET at 150V DC Bias.

It can be seen, that the measured data differs quite a bit from the manufacturer model.

Ceralink capacitors (TDK)

Ceralink is the name of a ceramic capacitor family manufactured by TDK which has its maximum capacity not at 0V DC bias but usually in the upper third of the DC voltage rating. The capacity itself and the DC bias voltage where the maximum occurs are significantly temperature dependent. They are designed to offer the highest capacitance at a defined operating voltage, e.g. at 400V for a 500V rated capacitor, illustrated in figure 3.1. The ceramic material used is lead lanthanum zirconium titanate (PLZT). Primary applications are high-frequency and power electronics.

TDK offers separate SPICE models of its Ceralink capacitors, valid for either time or frequency domain. Both models account for changes in capacity depending on temperature, DC bias and AC amplitude. In the time domain model, the ESR is also made dependent on the frequency.

In the figure below, the subcircuit, reconstructed from the accessible netlist, of the Ceralink capacitor (Partnumber: B58031I5105M062) time domain-model can be seen. The connectors to the outside are A1 and A2.

The function F1 for the behavioral voltage source B1 is V=V(B1,mid)*V(B1,mid), whereas the function F2 for B2 is V=limit(sqrt(V(int,A2)),0.5,7.1). The limits of 0.5V and 7.1V respectively are technical limits for the superimposed AC voltage of the time domain model. It covers small and intermediate signal behavior.

Finally, the expression F3 for B3 takes care of the temperature dependence and implements the component law of the capacitor. The equation is very lengthy and would cover a whole page. Generally said, function F3 looks like this I = C *ddt(V(B1, B2))

A structure of multiple paralleled, serial RC circuits is visible in the left area. This structure is reminiscent of the TDK ”precise model” for conventional MLCCs shown in the beginning. By varying the values (probably aided by automated procedures) of the components involved, a certain ESR(f) characteristic can be obtained.

The RL series circuit following afterwards is extended by a behavioral current source, paralleled by an RC low pass. The cut-off frequency is predefined as parameter statement fg=10 to determine internal voltages used in the equations of the behavioral sources.

The capacitance versus DC Bias behavior can again be expressed using a charge equation approach. A polynom is again fitted between certain data points of Capacitance and DC voltage using Matlab curve fitting toolbox. After sufficient matching, the polynom is integrated regarding the voltage to get an expression for the charge. This charge equation can then be written directly into LTspice in order to simulate the specific capacitance vs voltage characteristic of the component.

This has been done with both a third and eighth polynomial and compared to the original TDK model.

In the figure below, the schematic for this setup, including the charge equation for C2 at the bottom, can be seen.

Using a square pulse at the input, the output behavior displayed in the plot below can be observed.

The established manufacturers choose different topologies and structures when modelling their ceramic capacitors. Some are more, some less complex. By no means all voltage-, temperature- or frequency-dependent effects are modelled. Often they are negligible in real terms and are saved for the benefit of simpler models and faster simulation times. Nevertheless, accurate models in the time domain are very interesting, especially for simulations of conducted emissions and disturbances. The use of special ceramics as dielectrics requires models that can also reproduce their special properties. In addition to modelling with charge equations and lumped elements, voltage-controlled current sources are also suitable. They often contain long mathematical expressions.